This invention relates generally to semiconductors, and more particularly, to semiconductor circuitry implementation and operation for Dynamic Random Access Memory (DRAM) cells, which improve over the above-identified Application by permitting more compact cellular arrays and immediate detection of a Single Event Upset (SEU) in order to eliminate the need for elaborate error detection and correction schemes.
In a dynamic memory, the presence or absence of an electrical charge on a storage element, such as a capacitor, can represent either of two binary states. The dynamic memory is randomly accessible if it can be interrogated without requiring sequential addressing.
My prior U.S. Pat. Nos. 3,513,365 and 3,634,825 disclose Dynamic Random Access Memory (DRAM) cells in which two transistors are used as crosspoints for non-destructive readout, or as an associative memory using two cells per stored bit (binary digit). My pending application Ser. No. 08/265,463 reduced the number of access lines per cell to improve cell packing density.
However, these prior efforts do not solve the problems created by the universal presence of ionizing particles, such as alpha particles from radioactive contamination of packaging materials or cosmic radiation. Such particles destroy the information stored in a memory cell by creating temporary ionized tracks which uncontrollably charge or discharge a memory cell.
Events which obliterate the information stored in a memory cell are designated as Single Event Upsets (SEUs). To partially deal with this problem, data have been stored in groups of cells with error detection and correction capability, thus requiring extra storage capacity. As a result there is a reduction in effective cell packing density. There also is the requirement of elaborate systems for sweeping the memory to detect SEUs and make correction before there have been so many occurrences that correction cannot take place.
Various systems have been provided for dealing with SEUs in DRAM cells. These systems are disclosed in the following U.S. patents, which are incorporated herein by reference: U.S. Pat. No. 4,360,900 issued to Bate; U.S. Pat. No. 4,494,217 issued to Suzuki et al.; U.S. Pat. No. 4,891,684 issued to Nishioka et al.; and U.S. Pat. No. 4,937,650 issued to Shinriki et al.
Bate discloses using high dielectric constant insulators, such as those provided by zirconium oxide, hafnium oxide and tantalum oxide. High dielectric constant insulators are used in place of customary silicon oxide as part of the gate dielectric in field-effect transistors.
Suzuki et al. use an alpha shield of resinous material to protect semiconductor memories against "soft errors". This shields against alpha particles from packaging materials containing trace amounts of uranium or thorium.
In Shinriki et al., an insulating film is formed beneath a film of high dielectric-constant tantalum oxide to provide a large-capacity semiconductor capacitor for increased reliability.
Nishioka et al. disclose a semiconductor device with a reaction-preventing film between a capacitor insulator of tantalum oxide and an upper electrode to prevent a reaction between the electrode and the insulator.
The above-cited references approach error prevention by shielding, which cannot be effective for cosmic rays, or by increasing storage capacity with high dielectric constants or very thin insulators. This procedure becomes ineffective as geometries are reduced and, in any event, only reduces the likelihood of error occurrences without providing for their identification or correction.
It is an object of the invention to detect error producing "single event upset" events (SEUs).
Another object of the invention is to provide a dynamic random access memory with the capability for immediately indicating both when and where a single event upset has occurred.